@er1n Oh you mean the "yield my_sig"/"yield my_sig.eq(0)" constructs that interface to the simulation between clock ticks? Yea, that's cool!
A long time ago, migen used to call out to iverilog via VPI. Adding verilog functionality back into the current Python-based simulator isn't trivial, but I forget why.
@cr1901 yeah, i'm (thankfully!) not in a position to need full iverilog simulation, haha
@er1n Do you host your migen samples anywhere (just curious!)?
@cr1901 not up on github yet, but it will be!
@er1n The most valuable part of migen for me is the build system abstraction, followed closely by "generating Verilog code that avoids stuff like missing cases, uninitialized signals, async reset", and then easy FSM (the right way!) generation :).
If ppl give me hardware I'll port their board to Migen lmao
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