@er1n What's cosimulation (just another word for "using a Verilog simulator")?
Also, cool... a UART! I think...
@cr1901 cosimulation == some testbench code running in tandem with your simulation and poking at it
@er1n Do you host your migen samples anywhere (just curious!)?
@cr1901 not up on github yet, but it will be!
@er1n The most valuable part of migen for me is the build system abstraction, followed closely by "generating Verilog code that avoids stuff like missing cases, uninitialized signals, async reset", and then easy FSM (the right way!) generation :).
If ppl give me hardware I'll port their board to Migen lmao
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