Erin 🕯 @er1n@social.mecanis.me
undergrad with a sharpie
bring her coffee. she's probably tired.
cybre∧eecs∧DSP nerd∧cranky ML girl∧maths∧graphics shit
follow∥boost ≠endorsement of a user
😶
tfw no clown gf
why even live
psa: don't post screenshots of wifi lists from your phone / computer on the internet unless you're okay with people knowing where you are
that list of nearby wifi names can be used to pinpoint you with scary accuracy sometimes
in case anyone was actually interested in an actual mostly-assembled supercomputer on Craigslist it'll cost a lot more for a lot less raw compute but here ya go
https://seattle.craigslist.org/sno/sys/d/intel-paragon-xp-supercomputer/6605182173.html
did you know? if you write xbox backwards it spells "ps2 sucks"
you come into MY timeline and post HDL? first of all, how dare you
@amphetamine @MightyPork no, it's not verilog. it's python code using migen, which can generate either
ODIN (lines)
Work is coming along with this image.
Made live at: www.twitch.tv/oabnormal
@amphetamine yeah i'm just confused b/c whitequark did this in an example:
self.comb += tx_strobe.eq(tx_counter == 0)
self.sync += \
If(tx_counter == 0,
tx_counter.eq(divisor - 1)
).Else(
tx_counter.eq(tx_counter - 1)
)
note the first line
yall i have a fpga question
so if i have a synchronous counter that i'm using for clock division, is it okay to make the comparator generating the clock combinatorial, or should it be part of the synchronous logic (think always @(posedge ...)) that's doing the counting?
"It's dangerous weather out but also there's some sick shit out there so idk...."
🙄 😶
this shaved furby looking motherfucker
gODS PANDAS IS BAD
GAY: ★★★★★★★★★★★★★★★
